ElemRV - End-to-end Open-Source RISC-V Microcontroller
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Oct 1, 2026 - Scala
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open-source-silicon
Here are 99 public repositories matching this topic...
Three-arm ring-oscillator PUF on a Tiny Tapeout 2x2 tile (sky130): how much of the response is decided before fabrication. Pre-silicon.
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Oct 29, 2026 - Verilog
NumPy → streaming ISP hardware (Verilog) compiler
fpga hls numpy image-processing rtl verilog isp switchboard high-level-synthesis image-signal-processor hardware-design open-source-silicon
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Sep 9, 2026 - Python
Tiny tapeout gf180 ocd sram test for the gf0p3 shuttle
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Jun 18, 2026 - Verilog
Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.
docker magic asic container eda vlsi yosys semiconductor klayout netgen ngspice gdsii physical-design openroad sky130 chip-design gf180mcu open-source-silicon rtl-to-gdsii vyges
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Oct 29, 2026 - Dockerfile
Cognitive Direct-RF Sampling Transceiver: Massively pipelined SDR DSP baseband engine hardened on SkyWater 130nm for Efabless Caravel OpenMPW tapeout. 100-phase SystemVerilog RTL, OpenLane ASIC signoff, and 100% regression verified.
asic dsp sdr fft transceiver systemverilog digital-signal-processing viterbi caravel wishbone qam hardware-verification tapeout efabless openlane open-source-silicon skywater130 rf-dsp
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Oct 11, 2026 - Verilog
Beginner-friendly, Docker-based starter kit for designing a GF180MCU chip from RTL to a manufacturable GDSII — simulate, verify, and harden a working example, then make it yours and submit it to a wafer.space shuttle.
asic docker-compose eda gds open-source-hardware systemverilog-hdl gdsii asic-verification tapeout openroad gf180mcu open-source-silicon gf180 librelane wafer-space tepeout-tools
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Jul 3, 2026 - SystemVerilog
Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.
rust asic digital eda semiconductor silicon opendb signoff static-timing-analysis physical-design signal-integrity open-source-silicon eda-tools vyges sign-off open-silicon vyges-loom
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Oct 30, 2026 - Rust
This project implements a tetrahedral oscillator inspired by the paper “Analysis and Design of a Tetrahedral Oscillator” by Richelle L. Smith and Thomas H. Lee. The oscillator is built from coupled inverter pairs, and its operating frequency is tuned by adding capacitive loads to the internal nodes.
spice gds oscillator mixed-signal cmos custom-layout ngspice ring-oscillator lef sky130 xschem magic-vlsi analog-ic open-source-silicon tiny-tapeout
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May 7, 2026 - Python
Design-rule check: a GDS layout + a rule deck in, geometry violations out.
rust asic digital analog eda semiconductor mixed-signal opendb signoff gdsii physical-design physical-verification open-source-silicon design-rule-check eda-tools vyges open-silicon vyges-loom
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Oct 30, 2026 - Rust
Open-source subthreshold VGA core for hearing-aid audio compression — SKY130, gm/ID-driven flow. IEEE SSCS Code-a-Chip ISSCC'27 submission
open-source analog-ic-design sky130 gm-id analog-ic open-source-silicon gm-id-methodology sky130a analog-ic-layout sky130-pdk ieee-sscs
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Oct 29, 2026 - Jupyter Notebook
A 12-track height standard cell library built in SKY130 PDK. It is made up of 12 combinational cells, which were designed using Magic VLSI Layout Tool and characterized using
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Aug 11, 2026 - Python
Open-source waveguide mode analysis software
python simulation eda photonics silicon-photonics waveguide photonic-mode-solver mode-solver mode-analysis photonic-circuit integrated-photonics open-source-silicon eigenmode-solver photonic-design
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May 12, 2026 - Python
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
eda verilog systemverilog semiconductor cocotb browser-ide github-codespaces chip-design open-source-silicon vyges vyges-ip vybox vybox-lite
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Feb 20, 2026 - JavaScript
Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.
rust asic digital analog eda semiconductor mixed-signal silicon lvs opendb signoff physical-design open-source-silicon eda-tools vyges open-silicon vyges-loom layout-vs-schematic
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Oct 30, 2026 - Rust
8-bit synchronous counter taken from Verilog RTL to GDSII on SCL's 0.8 µm open PDK using OpenLane. Zero DRC violations, LVS matched, timing closed at ~120 MHz.
asic verilog vlsi yosys klayout lvs dvs physical-design openroad openlane open-source-silicon rtl-to-gdsii scl-pdk
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Oct 3, 2026 - Verilog
VyomansLab — VLSI design projects website: RTL-to-GDSII flow tutorials for traffic-light FSM and counter designs using Icarus Verilog, Yosys, OpenROAD and Nangate45 PDK.
eda verilog vlsi yosys iverilog digital-design physical-design openroad open-source-silicon rtl-to-gdsii nangate45
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Sep 22, 2026 - HTML
Logic restructuring on an AIG, every rewrite checkable for equivalence.
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Oct 30, 2026 - Rust
Pinned slang (SystemVerilog compiler) built with Bazel into one static archive, behind a small C shim and a safe Rust API.
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Oct 30, 2026 - C++
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