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1. caravel-direct-rf caravel-direct-rf Public

   Cognitive Direct-RF Sampling Transceiver: Massively pipelined SDR DSP baseband engine hardened on SkyWater 130nm for Efabless Caravel OpenMPW tapeout. 100-phase SystemVerilog RTL, OpenLane ASIC sig…

   Verilog 3

2. sby sby Public

   Forked from YosysHQ/sby

   SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

   Python

3. yosys yosys Public

   Forked from YosysHQ/yosys

   Yosys Open SYnthesis Suite

   C++

4. verilator verilator Public

   Forked from verilator/verilator

   Verilator open-source SystemVerilog simulator and lint system

   SystemVerilog

5. verilator/verilator verilator/verilator Public

   Verilator open-source SystemVerilog simulator and lint system

   SystemVerilog 4k 960