adpll

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

All Digital Phase-Locked Loop (ADPLL)

Two-tile all-digital PLL taped out on TinyTapeout SKY26c (SkyWater 130nm). Ring-oscillator DCO, counter-based TDC, PI loop filter. Locks 10 MHz reference to programmable output frequency up to 63x.

An All-Digital PLL (UMC 180nm) with a 25th-order FIR digital loop filter whose coefficients are trained by an ANN — achieving 2.26 GHz output, 8 ns lock time, and 5.3 mW power.

All-Digital PLL with Vernier TDC — Silicon Game | SSCS Chipathon 2026