systemverilog-assertions

This Repository contains the verification of a Synchronous FIFO design using SystemVerilog and SystemVerilogAssertions

[DAC 2026] QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis

✅ Formal verification of a 16-bit SIMD processor

Formal proof that your SystemVerilog assertions hold for all inputs — or the exact cycle that breaks them. Signed proof certificates + safety margins. Trial: sva-verify, SDK, benchmarks & evidence.

A Formal Verification frontend for Z3 Solver written in Go

SystemVerilog verification of an AXI4-Lite Slave featuring constrained-random testing, SVA, self-checking scoreboard, and protocol compliance.

RV32I RISC-V core written in SystemVerilog, with an emphasis on coverage-driven verification using constrained-random stimulus, SVA assertions, and functional coverage

Parameterisable dual-clock FIFO in SystemVerilog: Gray-pointer CDC, bound SVA, 8-config self-checking regression (xsim + Icarus), and the Vivado CDC constraints. Placed and routed on ZCU104.

AXI4-Lite slave RTL design and UVM-based verification using SystemVerilog, constrained-random testing, SVA, and functional coverage.

SystemVerilog verification of an 8-bit × 16 synchronous FIFO using a class-based testbench, scoreboard, and 10+ SVA assertions.

A simple tool that converts hardware specification text into SystemVerilog Assertions using an LLM.

Parameterized serial router with cycle-compatible SystemVerilog RTL, reusable UVM 1.2 verification, assertions, coverage closure, differential testing, and mutation analysis.

Формальная и функциональная верификация переходника с интерфейса valid-ready на интерфейс valid-credit.

Verilog I2C target controller verified with a cocotb/Verilator testbench: functional coverage, bound SVA, and mutation testing

End-to-end UART TX/RX verification using SystemVerilog OOP, constrained-random stimulus, functional coverage, SVA assertions, mailboxes, monitors, drivers, and self-checking scoreboards.

Floating point multiplier with rounder, exception handler and assertions in SystemVerilog. Project is part of class HW-2, ECE AUTH.

12-bit SPI Master-Slave RTL design with class-based SystemVerilog verification, SVA, and functional validation.

Programmable 4-tap FIR DSP accelerator on Artix-7 FPGA, built in SystemVerilog with pipelined fixed-point arithmetic, UART coefficient updates, and a Python GUI for waveform visualization and hardware verification.

Parameterized asynchronous FIFO in SystemVerilog with Gray-code pointers, 2-flop CDC synchronizers, and a self-checking SVA/coverage-driven testbench.

Parameterized dual-clock asynchronous FIFO designed in Verilog for safe Clock Domain Crossing (CDC). Implements Gray-code pointer encoding, 2-flip-flop synchronizers, and conservative full/empty flag logic following Cummings SNUG 2002 architecture. Verified with a 600-line self-checking reference testbench and SVA protocol assertions across 7 test.