【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
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Jul 12, 2020 - Coq
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sdram-controller
Here are 20 public repositories matching this topic...
Verilog HDL implementation of SDRAM controller and SDRAM model
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Jun 19, 2024 - Verilog
SDRAM controller optimized to a memory bandwidth of 316MB/s
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Aug 16, 2021 - Verilog
Simple SDRAM Controller for DE10-Lite.
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Jan 20, 2019 - Verilog
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
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Jul 8, 2021 - Verilog
A HDL SDRAM controller designed for retro hardware and FPGAs
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Jun 25, 2023 - SystemVerilog
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
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Sep 26, 2026 - HTML
SDRAM Tester implemented in FPGA
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May 1, 2021 - VHDL
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
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Oct 30, 2017 - Verilog
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
python flash makefile verification uart risc testbench sdram sdram-controller cocotb cocotb-testing design-verification
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Oct 15, 2023 - Verilog
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller
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Oct 21, 2024 - Verilog
SDR SDRAM Controller with Avalon-MM bus
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Apr 11, 2022 - Verilog
High-Speed SystemVerilog SDRAM Controller
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Jan 27, 2024 - SystemVerilog
🛠 A SDRAM controller in Verilog HDL
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Mar 21, 2022 - Verilog
RISC-V (Nios V) SoC para placas genéricas Cyclone IV (EP4CE6, EP4CE10, EP4CE15) com controlador SDRAM, bootloader via SPI e módulo PWM (com Testbench) em VHDL
fpga vhdl fpga-soc risc-v cyclone-iv ep4ce6e22c8n nios-embedded-system sdram sdram-controller vhdl-examples vhdl-testbench pwm-controller ep4ce6 niosv ep4ce15 risc-v-processor quartus-prime-lite ep4ce6f17c8 ep4ce22 nios-v
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Aug 19, 2026 - SystemVerilog
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May 9, 2026 - C
Overview: The goal of this project is to design an SDRAM controller that allows SDRAM memory to be interfaced with a microprocessor having only asynchronous memory support. There is no requirement to build the hardware, but a complete written report containing schematics and theory of operation is required
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Oct 10, 2020
DESIGN AND IMPLEMENTATION OF 64-BIT SRAM AND SDRAM POWER OPTIMIZED CONTROLLER
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Mar 21, 2026
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