axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

AMBA AXI VIP

Code generation tool for control and status registers

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

A Fast, Low-Overhead On-chip Network

Control and status register code generator toolchain

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Network on Chip Implementation written in SytemVerilog

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

An open-source HDL register code generator fast enough to run in real time.

PCIe DMA-based external game state reader. Hardware DMA capture, memory layout discovery, no in-process injection. C#

PCIe DMA-based external game state reader. Hardware DMA capture, memory layout discovery, no in-process injection. C#

Simple single-port AXI memory interface

Xilinx AXI VIP example of use

Agent-ergonomic CLI for TypeSafe's Jev: fast calibrated judgments (pick, rate, check, rank, triage, guard) from the shell

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

OPAE porting to Xilinx FPGA devices.

Xilinx PCIe to MIG DDR4 example designs and custom part data files

数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经