vyges-tools repositories

ihp-open-pdk

Public

Vyges mirror of IHP-Open-PDK — tracks the dev branch, where the SG13CMOS-5L overlay lives beside the SG13G2 base in ONE tree (one commit pin; the overlay symlin…

asic semiconductor pdk

asic semiconductor pdk open-source-silicon

Python

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

icsprout55

Public

Vyges mirror — icsprout55

asic semiconductor pdk

asic semiconductor pdk open-source-silicon

Verilog

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

vyges-openroad

Public

Reproducible builds of mainline OpenROAD — slim container + relocatable binary

rust container eda

rust container eda reproducible-builds physical-design openroad open-source-silicon

Shell

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

cli

Public

Public release home for the Vyges CLI — prebuilt binaries + curl/PowerShell installers (catalog, PDK, and Loom-engine installs). Homebrew tap: vyges/homebrew-ta…

rust cli installer

rust cli installer eda semiconductor silicon ic-design hardware-design open-source-silicon vyges

0•0•0•0•Updated

Oct 31, 2026

suite

Public

The Vyges engines as two binaries: vyges-loom and vyges-physical

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

syn

Public

Integrated logic synthesis from RTL to a mapped netlist.

rust asic eda

rust asic eda systemverilog logic-synthesis aig opendb physical-design open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

psm

Public

Power-grid analysis on the design database: connectivity check, static IR drop, SPICE export.

rust asic eda

rust asic eda physical-design power-integrity power-grid electromigration ir-drop open-source-silicon vyges

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

rmp

Public

Logic restructuring on an AIG, every rewrite checkable for equivalence.

rust asic eda

rust asic eda abc logic-synthesis aig opendb physical-design logic-optimization open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

cts

Public

Clock tree synthesis of a placed design: clock buffers chosen, every clock net found and its sinks collected, clock gaters cloned.

rust asic eda

rust asic eda opendb physical-design place-and-route open-source-silicon clock-tree-synthesis

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

dft

Public

Scan insertion and stitching, so a chip can be tested after fabrication.

rust asic dft

rust asic dft eda physical-design scan-chain design-for-test open-source-silicon scan-insertion vyges

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

rsz

Public

Electrical repair of a placed design: repeaters along each net's Steiner tree and driver resizing, wherever a wire is too long or a capacitance, fanout or trans…

rust asic eda

rust asic eda opendb static-timing-analysis physical-design place-and-route timing-closure open-source-silicon buffer-insertion

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

grt

Public

Global routing in Rust: FastRoute over a placed OpenDB design, route guides, layer assignment, incremental routing and antenna repair.

rust asic routing

rust asic routing eda opendb physical-design place-and-route global-routing open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

upf

Public

Power intent (UPF) for designs with several power domains.

rust asic eda

rust asic eda isolation low-power upf level-shifter physical-design open-source-silicon vyges

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

gpl

Public

Global placement: the placer's view of the design and the bound-to-bound initial placement, bit-exact.

rust asic eda

rust asic eda opendb physical-design place-and-route global-placement open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

drt

Public

Detailed routing, starting with pin access: every pin's access points and each routed terminal's preferred point, reproducible bit for bit

rust asic eda

rust asic eda opendb physical-design open-source-silicon pin-access detailed-routing

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

est

Public

Parasitic estimation from placement: Steiner-tree RC networks per corner, written as SPEF.

rust asic eda

rust asic eda opendb spef static-timing-analysis physical-design open-source-silicon parasitics

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

dpl

Public

Detailed placement over the OpenDB design database: placement legality checking.

rust asic eda

rust asic eda opendb physical-design place-and-route legalization open-source-silicon detailed-placement

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

fin

Public

Density fill over the OpenDB design database: metal fill shapes to meet per-layer density rules

rust asic eda

rust asic eda opendb drc physical-design open-source-silicon density-fill

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

pad

Public

IO pad and bump placement over the OpenDB design database: the pad ring, its cells, and the bump array

rust asic packaging

rust asic packaging eda opendb physical-design open-source-silicon io-pads

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

ppl

Public

IO pin placement over the OpenDB design database: slots, optimal matching, constraints, groups, mirrored pins, top layer, and simulated annealing

rust asic eda

rust asic eda opendb physical-design floorplanning place-and-route open-source-silicon pin-placement

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

pdn

Public

Power distribution network generation over the OpenDB design database

rust asic eda

rust asic eda opendb physical-design power-distribution-network power-grid open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

tap

Public

Row cutting and physical-cell insertion over the OpenDB design database: tap cells, endcaps, corners

rust asic eda

rust asic eda opendb physical-design standard-cell open-source-silicon tapcell endcap

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

mpl

Public

Hierarchical macro placement: clustering, coarse shaping, annealing, boundary push, orientation, commit and track snapping, over the OpenDB database.

rust asic eda

rust asic eda vlsi silicon opendb physical-design floorplanning place-and-route open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

ifp

Public

Floorplan initialization over the OpenDB design database: die/core area, site-grid snapping, and rows

rust asic eda

rust asic eda opendb physical-design floorplanning place-and-route open-source-silicon

Rust

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Apache License 2.0

•0•0•0•0•Updated

Oct 31, 2026

ant

Public

Antenna ratio sign-off over the routed design database: PAR/CAR/PSR/CSR per layer against the LEF limits, including the diffusion-dependent (PWL) form.

rust asic eda

rust asic eda antenna opendb signoff drc physical-design open-source-silicon antenna-rules

Rust

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Apache License 2.0